A Power Optimization Toolbox for Logic Synthesis and Mapping

The paper describes several complementary algorithms for power-aware logic optimization: o SimSwitch is an efficient sequential simulator for estimating switching activity of signals in large sequential designs. o PowerMap uses switching activity to make better decisions during power-aware technology mapping. o PowerDC is a resynthesis algorithm that eliminates wires with high switching activity. The proposed simulator draws on new ideas in logic representation and is geared for speed, e.g. it can simulate a 1Mnode sequential design using 1000 bit patterns for 100 cycles in about 10 seconds on a typical one-core CPU. This is more than 85X faster than previously published activity estimators with similar accuracy. Experiments show that, although each technique contributes to the final quality, it is their combination that gives the best results. When applied to large industrial designs in a highly-optimized industrial flow, previous work on sequential synthesis and wire-aware technology mapping led to a 27.6% reduction in switching activity, while the techniques of this paper reduce it additionally by 19.6% without a substantial increase in runtime or degradation of other metrics.